Fairly complex electronic circuits are very difficult to test. Currently, it is not possible to stimulate a semiconductor device from its perimeter pads with the one-hundred percent confidence that every single node of the device will be exercised. Generally, the best fault coverage (the number of nodes testable divided by the number of nodes total) is around 90 to 95 percent. And, even with the best fault coverage, there is still a significantly non-negligible probability that although the device may pass the fault screening that it still may not work.
One of the historical difficulties has been that there is a limited amount of surface area on the perimeter of a given device. Since most of the perimeter surface area for complex electronic circuits is used for pads required for operation of the device, very little perimeter space can be allocated strictly for fault detection purposes. In designing semiconductor devices, it has always been desirable but not feasible to provide for additional test pads to be used to probe and interrogate all the nodes including those normally not interrogated which are internal to the device.
A new problem which is starting to arise is that RAM is being incorporated in greater amounts in complex logic circuits. It is not possible to have enough perimeter pads to test the high density RAM with the number of pads required for the complex logic circuitry. It is, however, possible to test using circuitry incorporated in the device itself, but the results of the fault detection must still be made available to the outside through additional pads.
An interesting alternative has been to include circuitry to test the RAM and instruct the RAM to repair itself using a number of different mechanisms. The mechanisms used would depend on where the fault is located and its nature. However, it is still necessary to be able to know, outside the device, the number and nature of the self-repairs in order to control the quality of the manufacturing process. It may well be that the problems which are being self-repaired are those which should be prevented by changes in the manufacturing process rather than through fault detection. This would result in a higher reject rate, or lower yield, than necessary. In any event, additional perimeter pads are still required to bring the information to the outside.
Another minor problem which existed in the prior art is that the temperature at which the tests are run will not necessarily correspond to the temperature at which a device will operate. Thus, while the device would pass the probe tests, this would be no assurance that the device would operate properly in actual operation.
One solution to the above involves electron beam (E-beam) probing. E-beam probing is well known in the fault detection field where a primary electron beam irradiates locations on a semiconductor and secondary electron emissions from the locations are measured to determine the potential at such locations.
In this solution, E-beam probing is coupled with non-perimeter test pads. The surface area test pads are incorporated into the layout of the device die to propagate upward through the structure of the device die from particular nodes to the top layer of the die under the passivation layer. Electron beams played on the surface of operating die are able to probe at the test pad locations for various potentials. This is especially true when the device is put into a characterized state. The characterized state is defined as where the device is powered and the input/output convention is specified; it is not necessary that the device be clocked at full operating speed.
While the above is an elegant solution, it has a number of drawbacks. The one major problem is that an electron beam will only work in a relatively hard vacuum. This means that testing of wafers or die must be done in a vacuum chamber large enough to contain the wafers or die. This requirement of a large vacuum chamber means a great deal of time is required to pump down to the hard vacuum, approximately 10.sup.-6 torr at which the electron beam will operate. This slows the processing of wafers and die significantly.
This solution has the attendant problem of requiring additional handling for the devices in and out of the vacuum chamber and resultant breakage.
Another problem is that each different semiconductor device requires a custom probe pad system for establishing the characterize state in the particular device. Still further, the custom probe pad system must be capable of working in a hard vacuum and there must be an arrangement for wiring out the custom probe pad systems to the outside of the vacuum chamber to the control system.
The correction of the located faulty circuitry in the devices has always been a separate operation from fault detection. Thus, the correction of faulty circuitry requires additional handling for the semiconductor devices to be placed in fault correction equipment such as laser trimming or cutting systems. In addition to handling, absolutely accurate placement of the devices were required in both the fault detection equipment and the fault correction equipment to insure that the fault correction equipment was performing the proper correction to the proper location. Finally, the semiconductor devices would have to be reinserted in the fault detection equipment to make sure the faults were actually corrected.
Another problem resulting from testing, followed by correction, followed by testing is that the test probe wires make an indentation on initial contact with the test pads which may cause problems on a second contact. Thus, although a correction is made, the second testing may have false errors introduced by the second testing itself.
A solution for solving these various problems has been long sought by but elusive to those skilled in the art.